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MC10136 Universal Hexadecimal Counter
The MC10136 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications, and the synchronous count feature makes the MC10136 suitable for either computers or instrumentation. Three control lines (S1, S2, and Carry In) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out goes low on the terminal count, or when the counter is being preset. This device is not designed for use with gated clocks. Control is via S1 and S2. * PD = 625 mW typ/pkg (No Load) * fcount = 150 MHz typ * tpd = 3.3 ns typ (C-Q) * 7.0 ns typ (C-Cout) * 5.0 ns typ (Cin-Cout)
DIP PIN ASSIGNMENT
VCC1 Q2 Q3 Cout D3 D2 S2 VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q1 Q0 CLOCK D0 D1 Cin S1 MC10136P MC10136FN PDIP-16 PLCC-20 25 Units / Rail 46 Units / Rail A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
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16 CDIP-16 L SUFFIX CASE 620 1 16 PDIP-16 P SUFFIX CASE 648 1 1 PLCC-20 FN SUFFIX CASE 775 10136 AWLYYWW MC10136P AWLYYWW MC10136L AWLYYWW
ORDERING INFORMATION
Device MC10136L Package CDIP-16 Shipping 25 Units / Rail
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
FUNCTION TABLE
Cin X L H L H X S1 L L L H H H S2 L H H L L H Operating Mode Preset (Program) Increment (Count Up) Hold Count Decrement (Count Down) Hold Count Hold (Stop Count)
(c) Semiconductor Components Industries, LLC, 2002
1
January, 2002 - Rev. 7
Publication Order Number: MC10136/D
MC10136
LOGIC DIAGRAM
S1 9
S2 7 Carry In 10
VCC1 = PIN 1 VCC2 = PIN 16
T T Clock 13 Q0 Q0 C T T Q1 Q1 TC T T Q2 T Q3 T T Q3 TT C
VEE = PIN 8
T Q2 TC
12 D0
14 Q0
11 D1
15 Q1
6 D2
2 Q2
5 D3
3 Q3
4 Carry Out
NOTE: Flip-flops will toggle when all T inputs are low.
SEQUENTIAL TRUTH TABLE*
INPUTS S1 L L L L L L H L H H H H S2 L H H H H H H L L L L L D0 L X X X X X X H X X X X D1 L X X X X X X H X X X X D2 H X X X X X X L X X X X D3 H X X X X X X L X X X X Carry In X L L L H H X X L L L L Clock ** H H H H L H H H H H H H Q0 L H L H H H H H L H L H Q1 L L H H H H H H H L L H OUTPUTS Q2 H H H H H H H L L L L H Q3 H H H H H H H L L L L H Carry Out L H H L H H H L H H L H
* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom. ** A clock H is defined as a clock input transition from a low to a high logic level.
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MC10136
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 5,6,11,12 7 9,10 13 All 14 (2.) 14 (2.) 14 (2.) 14 (2.) 0.5 -1.060 -1.890 -1.080 -1.655 -0.890 -1.675 -30C Min Max 138 350 425 390 460 0.5 -0.960 -1.850 -0.980 -1.630 -0.810 -1.650 Min +25C Typ 100 Max 125 220 265 245 290 0.3 -0.890 -1.825 -0.910 -1.595 -0.700 -1.615 +85C Min Max 138 220 265 245 290 Unit mAdc Adc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) t13+14+ t13+14- t13+4+ t13+4- t10-4- t10+4+ t12+13+ t12-13+ t9+13+ t7+13+ t10-13+ t10+13+ t13+12+ t13+12- t13+9+ t13+7+ t13+10- t13+10+ fcountup fcountdown t4+ t14+ t4- t14- VOH VOL VOHA VOLA
Adc Vdc Vdc Vdc Vdc ns
Propagation Delay Clock Input
14 14 4 4 4 (3.) 4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 4 14 4 14
0.8 0.8 2.0 2.0 1.6 1.6 3.5 3.5 6.0 6.0 2.5 1.5 0 0 -1.0 -1.0 0 0 125 125 0.9 0.9 0.9 0.9
4.8 4.8 10.9 10.9 7.4 7.4
1.0 1.0 2.5 2.5 1.6 1.6 3.5 3.5 6.0 6.0 2.5 1.5 0 0 -1.0 -1.0 0 0 125 125
3.3 3.3 7.0 7.0 5.0 5.0
4.5 4.5 10.5 10.5 6.9 6.9
1.4 1.4 2.4 2.4 1.9 1.9 3.5 3.5 6.0 6.0 3.0 1.5 0 0 -1.0 -1.0 0 0
5.0 5.0 11.5 11.5 7.5 7.5
Carry In to Carry Out Setup Time Data Inputs Select Inputs Carry In Input Hold Time Data Inputs Select Inputs Carry In Input Counting Frequency Rise Time Fall Time (20 to 80%) (20 to 80%)
150 150 2.0 2.0 2.0 2.0 3.3 3.3 3.3 3.3
125 125 1.1 1.1 1.1 1.1 3.5 3.5 3.5 3.5
MHz ns
3.3 3.3 3.3 3.3
1.1 1.1 1.1 1.1
1. Individually test each input; apply VILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set all Q outputs to a logic high. 4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70C only when 500lfpm blown air or equivalent heat sinking is provided.
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MC10136
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 5,6,11,12 7 9,10 13 All 14 (2.) 14 (2.) 14 (2.) 14 (2.) +1.11V t13+14+ t13+14- t13+4+ t13+4- t10-4- t10+4+ t12+13+ t12-13+ t9+13+ t7+13+ t10-13+ t10+13+ t13+12+ t13+12- t13+9+ t13+7+ t13+10- t13+10+ fcountup fcountdown (20 to 80%) (20 to 80%) t4+ t14+ t4- t14- 14 14 4 4 4 (3.) 4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 4 14 4 14 7 7 7 9 7 7 7 7 9 7 7 9 9 7, 9 7, 9 12 7 7 7 7 13 13 7, 9 7, 9 12 5,6,11,12 7 9,10 13 Note 1. 7, 9 7, 9 7, 9 7, 9 +0.31V Pulse In 13 13 13 13 10 10 12, 13 12, 13 9, 13 7, 13 10, 13 10, 13 12, 13 12, 13 9, 13 7, 13 10, 13 10, 13 13 13 13 13 13 13 12 12 Pulse Out 14 14 4 4 4 4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 4 14 4 14 VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Clock Input VOH VOL VOHA VOLA
Carry In to Carry Out Setup Time Data Inputs Select Inputs Carry In Inputs Hold Time Data Inputs Select Inputs Carry In Inputs Counting Frequency Rise Time Fall Time
1. Individually test each input; apply V ILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set all Q outputs to a logic high. 4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70C only when 500lfpm blown air or equivalent heat sinking is provided. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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MC10136
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C
VIN NOTE: tsetup is the minimum time before the positive transition of the clock pulse (C) that information must be present at the input D or S. thold is the minimum time after the positive tran sition of the clock pulse (C) that information must remain unchanged at the input D or S. INPUT PULSE T+ = T- = 2.0 0.2 NS (20 TO 80%) Clock COAX VCC1 = VCC2 = +2.0 VDC 25 F 1 CIN C D0 D1 D2 D3 S1 S2 16 Q0 Q1 Q2 Q3 COUT 8 0.1 F VEE = -3.2 VDC +1.11 V
thold L
VOUT COAX
0.1 F
CLOCK INPUT +1.11 V TPin
TPout
50% tC+Q+ tC+Q-
+0.31 V
Q Output
80% 50% 20% tQ+ 50%
thold H
tQ-
C
+0.31 V 50 ohm termination to ground lo cated in each scope channel input.
D or S tsetup H Q
50% tsetup L
All input and output cables to the scope are equal lengths of 50 ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. Unused outputs are connected to a 50 ohm resistor to ground.
CARRY IN
SET UP AND HOLD TIMES
Carry in tset (L) thold (L) tset (N) thold (N)
C
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MC10136
APPLICATIONS INFORMATION
To provide more than four bits of counting capability several MC10136 counters may be cascaded. The Carry In input overrides the clock when the counter is either in the increment mode or the decrement mode of operation. This input allows several devices to be cascaded in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between stages as shown with no external gating. The Carry In of the first device may be left open. The system clock is common to all devices. The various operational modes of the counter make it useful for a wide variety of applications. If used with MECL III devices, prescalers with input toggle frequencies in excess of 300 MHz are possible. Figure 2 shows such a prescaler using the MC10136 and MC1670. Use of the MC10231 in place of the MC1670 permits 200 MHz operation.
Figure 1. 12 BIT SYNCHRONOUS COUNTER
LSB Q0 Q1 Q2 Q3 Cin Cout Q0 Q1 Q2 Q3 Cin Cout MSB Q0 Q1 Q2 Q3 Cin
The MC10136 may also be used as a programmable counter. The configuration of Figure 3 requires no additional gates, although maximum frequency is limited to about 50 MHz. The divider modulus is equal to the program input plus one (M = N + 1), therefore, the counter will divide by a modulus varying from 1 to 16. A second programmable configuration is also illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up to 110 MHz typically. The divider modulus for this figure is equal to the program input (M = N). The minimum modulus is 2 because of the pulse swallowing technique, and the modulus may vary from 2 to 15. This programmable configuration requires an additional gate, such as 1/2MC10109 and a flip-flop such as 1/ MC10131. 2
Figure 2. 300 MHz PRESCALER
Logic High MC10136 S1 D Input Frequency C Q Q S2 C
C
C
C
Q3 Input Frequency 32
System Clock
NOTE: S1 and S2 are set either for increment or decrement operation.
MC1670
Figure 3. 50 MHz PROGRAMMABLE COUNTER
Figure 4. 100 MHz PROGRAMMABLE COUNTER
Program Input
Program Input fin C Cin S2 S1 D0 D1 D2 D3 Cout fout
fin
C S2 S1
D0 D1 D2 D3 MC10136 Q0 Q2 Q3
D 1/2MC10109 C 1/2MC10131
Q
fout
1 2
fout =
fin Program Input + 1
Q
fmax 50 MHz Typ. fin Program Input
3 Divide Ratio is from 1 to 16. 1 2 fout =
fmax 110 MHz Typ.
3 Divide Ratio is from 2 to 15.
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MC10136
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) 0.007 (0.180)
M
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10136
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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PUBLICATION ORDERING INFORMATION
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MC10136/D

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